veri log HDL codes in Quartus

-------------FOR Quartus 13.0sp1------------- reason for not getting proper waveform : 1)File name:     your file name must be your module name 2)Compilation:     Your must be code successfully Compiled . 3)Device :     During creating new project Wizard You must need to select proper device in 2nd step.     I recommended cyclon II device.     *If your modalism Altera software properly installed  then not need to go for any extra device 4)Project:     During simulation check you are in a project where your verilog HDL file saved If all the above steps are correct and then you also you get an error or after simulation you not get wave form see :  https://youtu.be/kZ-c-UGvPyk            after watching that your all error must will be solved . Thank you

//  -------------FULL ADDER------------ //equation of full adder //sum = a^b^cin //cout = ab + bcin + acin //-------------------------------------- //verilog HDL Code : module fulladder(a,b,cin,sum,cout); input cin, a, b; output sum,cout; wire z1,z2,z3,z4; and and1(z1,a,b); and and2(z2,b,cin); and and3(z3,a,cin); or(cout,z1,z2,z3); xor xor1(z4,a,b); xor(sum,z4,cin); endmodule RTL view : For More about this project see : https://youtu.be/550JKqcu9e8