Gate level modeling of full adder circuit .

// -------------FULL ADDER------------
//equation of full adder //sum = a^b^cin //cout = ab + bcin + acin //-------------------------------------- //verilog HDL Code : module fulladder(a,b,cin,sum,cout); input cin, a, b; output sum,cout; wire z1,z2,z3,z4; and and1(z1,a,b); and and2(z2,b,cin); and and3(z3,a,cin); or(cout,z1,z2,z3); xor xor1(z4,a,b); xor(sum,z4,cin); endmodule







RTL view :

For More about this project see : https://youtu.be/550JKqcu9e8




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