Verilog HDL code | 3X8 decoder using Conditional Operator

3X8 decoder using Conditional Operator


module con_3x8_DC(s,i);

input [0:2]s;

output [0:7]i;

assign i = ~s[0] ? ( ~s[1] ? (~s[2] ? 1 : 2):  (~s[2] ? 4 : 8)): ( ~s[1] ? (~s[2] ? 16 : 32):  (~s[2] ? 64 : 128));

endmodule

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